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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc. 4M x 4 CMOS DRAM
WITH FAST PAGE MODE, 5 VOLT
AVAILABLE AS MILITARY SPECIFICATIONS
* MIL-STD-883
Vcc DQ0 DQ1 W\ RAS\ NC
AS4C4M4
PIN ASSIGNMENT (Top View)
24 Pin TSOP (DG)
1 2 3 4 5 6 24 23 22 21 20 19 Vss DQ3 DQ2 CAS\ OE\ A9
FEATURES
* Fast Page Mode Operation * CAS\-before-RAS\ Refresh Capability * RAS\-only and Hidden Refresh Capability * Self-refresh Capability * Fast Parallel Test Mode Capability * TTL Compatible Inputs and Outputs * Early Write or Output Enable Controlled Write * JEDEC Standard Pinout * Single +5V (10%) Power Supply
A10 A0 A1 A2 A3 Vcc
7 8 9 10 11 12
18 17 16 15 14 13
A8 A7 A6 A5 A4 Vss
OPTIONS
* Timing 60ns access 70ns access * Package Plastic TSOP, 24-pin
MARKINGS
-6 -7
PIN ASSIGNMENT
PIN A0 - A10 DQ0 -DQ3 VSS FUNCTION Address Inputs Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power (+5V) No Connect
DG
* Operating Temperature Ranges Military (-55oC to +125oC) Industrial (-40oC to +85oC)
XT IT
RAS\ CAS\ W\ OE\ VCC NC
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS4C4M4DG is a 4,194,304 x 4 bit Fast Page Mode CMOS DRAM offering high speed random access of memory cells within the same row. This device features a +5V (10%) power supply, refresh cycle (2K), and fast access times (60 and 70ns). Other features include CAS\-before-RAS\, RAS\-only refresh, and Hidden refresh capabilities. This 4M x 4 Fast Page Mode DRAM is fabricated using an advanced CMOS process to realize high bandwidth, low power consumption and high reliability. It may be used as main memory for high level computers, microcomputers and personal computers.
PERFORMANCE RANGE
SPEED -6 -7 tRAC 60 70 tCAC 15 18 tRC 110 130 tPC 40 45 UNITS ns ns
For more products and information please visit our web site at www.austinsemiconductor.com
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM
RAS\ CAS\ W\ Control Clocks VCC VBB Generator VSS
AS4C4M4
Refresh Timer
Row Decoder
Data In Buffer
Sense Amps & I/O
Refresh Control Memory Array 4,194,304 x 4 Cells
Refresh Counter
DQ0 to DQ3
(A0 - A10)
Row Address Buffer
(A0 - A10)
Col. Address Buffer
Column Decoder
Data Out Buffer
OE\
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VCC (VIN, VOUT) .....-1.0V to +7.0V Voltage on VCC supply relative to VSS (VCC).........-1.0V to +7.0V Storage Temperature (Tstg)................................-55C to +150C Power Dissipation (PD).............................................................1W Short Circuit Output Current (IOS Address).........................50mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity (plastics).
ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TA < +125oC & -40oC < TA < +85oC ; Vcc = 5V +10%)
PARAMETER Supply Voltage Input High Voltage Input Low Voltage
NOTES: 1. VCC + 2.0V/20ns, Pulse width is measured at VCC 2. -2.0V/20ns, Pulse width is measured at VSS
SYMBOL VCC VIH VIL
MIN 4.5 2.4 -0.5
2
TYP 5.0 -----
MAX 5.5 VCC + 0.5 0.8
1
UNITS V V V
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
AS4C4M4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TA < +125oC & -40oC < TA < +85oC ; Vcc = 5V +10%)
PARAMETER Input Leakage Current (any input 0MAX SYMBOL ICC1* ICC2 ICC3* PARAMETERS Operating Current (RAS\ and CAS\, Address cycling @ tRC = MIN), Power = Don't Care Standby Current (RAS\ = CAS\ = W\ = VIH) Power = Normal L RAS\-only Refresh Current (CAS\ = VIH, RAS\, Address cycling @ tRC = MIN), Power = Don't Care Fast Page Mode Current (RAS\ = VIL, CAS\, Address cycling @ tPC = MIN), Power = Don't Care Standby Current (RAS\ = CAS\ = W\ = Vcc - 0.2V) Power = Normal L CAS\-BEFORE-RAS\ Refresh Current (RAS\ and CAS\ cycling @ tRC = MIN), Power = Don't Care Battery back-up current, Average power supply current, Battery backup mode, Input high voltage (VIH) = VCC - 0.2V, Input low voltage (VIL) = 0.2V, CAS\ = 0.2V, DQ = Don't care, tRC = 62.5us (2K/L-ver), tRAS = tRAS min ~ 300ns ICCS Self Refresh Current, RAS\ = CAS\ = 0.2V, W\ = OE\ = A0 ~ A11 = VCC - 0.2V or 0.2V, DQ0 ~ DQ3 = VCC - 0.2V, 0.2V or Open 1 1 -60 110 3 -70 100 3 UNITS mA mA
110
100
mA
ICC4* ICC5 ICC6*
90 2 110
80 2 100
mA mA mA
ICC7
1
1
mA
NOTES: *ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3, and ICC6 address can be changed maximum once while RAS\ = VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
CAPACITANCE (TA < +25oC ; Vcc = 5V +10%)
PARAMETER Input capacitance (A0 - A11) Input capacitance (RAS\, CAS\, W\, OE\) Output capacitance (DQ0 - DQ3) SYMBOL CIN1 CIN2 CDQ MAX 6 8 8 UNITS pF pF pF
AS4C4M4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS1,2 (-55oC-60 SYMBOL tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL PARAMETER Random read or write cycle time Read-modify-write cycle time Access time from RAS\ Access time from CAS\ Access time from column address CAS\ to output in Low-Z Output buffer turn-off delay Transition time (raise and fall) RAS\ precharge time RAS\ pulse width RAS\ hold time CAS\ hold time CAS\ pulse width RAS\ to CAS\ delay time RAS\ to column address delay time CAS\ to RAS\ precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS\ lead time Read command set-up time Read command hold time referenced to CAS\ Read command hold time referenced to RAS\ Write command hold time Write command pulse width Write command to RAS\ lead time Write command to CAS\ lead time 0 0 3 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 10K 45 30 10K 15 50 MIN 110 155 60 15 30 0 0 3 50 70 17 65 18 25 17 5 0 10 0 12 35 0 0 0 12 12 17 17 10K 50 35 10K 15 50 MAX MIN 130 185 70 20 35 -70 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 4 10 3, 4, 10 3, 4, 5 3, 10 3 6 2 NOTES
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
AS4C4M4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS1,2 (CONTINUED)
-60 SYMBOL tDS tDH tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tRASS tRPS tCHS Data set-up time Data hold time Refresh period Write command set-up time CAS\ to W\ delay time RAS\ to W\ delay time Column address to W\ delay time CAS\ precharge to W\ delay time CAS\ set-up time (CAS\-before-RAS\ refresh) CAS\ hold time (CAS\-before-RAS\ refresh) RAS\ to CAS\ precharge time Access time from CAS\ precharge Fast Page cycle time Fast Page read-modify-write cycle time CAS\ precharge time (Fast Page Cycle) RAS\ pulse width (Fast Page Cycle) RAS\ hold time from CAS\ precharge OE\ access time OE\ to data delay Output buffer turn off delay time from OE\ OE\ command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W\ to RAS\ precharge time (C\-B-R\ refresh) W\ to RAS\ hold time (C\-B-R\ refresh) RAS\ pulse width (C\-B-R\ self refresh) RAS\ precharge time (C\-B-R\ self refresh) CAS\ hold time (C\-B-R\ self refresh) 15 0 15 10 10 10 10 100 110 -50 15 40 85 10 60 35 15 17 0 17 10 10 10 10 110 120 -50 17 100K 0 40 85 55 60 5 10 5 35 45 95 10 70 40 17 100K PARAMETER MIN 0 10 32 0 45 90 60 65 5 15 5 40 MAX MIN 0 12 32 -70 MAX UNITS ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ns ns 13, 14, 15 13, 14, 15 13, 14, 15 11 11 6 3 7 7 7 7 NOTES 9 9
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
TEST MODE CYCLE11
-60 SYMBOL tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tCPWD tPC tPRWC tRASP tCPA tOEA tOED tOEH PARAMETER Random read or write cycle time Read-modify-write cycle time Access time from RAS\ Access time from CAS\ Access time from column address RAS\ pulse width CAS\ pulse width RAS\ hold time CAS\ hold time Column address to RAS\ lead time CAS\ to W\ delay time RAS\ to W\ delay time Column address to W\ delay time CAS\ precharge to W\ delay time Fast Page cycle time Fast Page read-modify-write time RAS\ pulse width (Fast Page Cycle) Access time from CAS\ precharge OE\ access time OE\ to data delay OE\ command hold time 20 20 65 20 20 65 35 45 90 60 65 45 90 65 100K 40 20 22 22 MIN 115 160 65 20 35 10K 10K 75 25 22 70 40 48 100 70 70 50 100 75 100K 45 22 MAX MIN 135 180 70 22 38 10K 10K -70 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 7 7 7 3, 4, 10, 12 3, 4, 5, 12 3, 10 ,12 NOTES
AS4C4M4
NOTES:
1. An initial pause of 200us is required after power-up followed by an 8 RAS\-only refresh or CAS\-before-RAS\ refresh cycles before proper device operation is achieved. 2. VIH(MIN) and VIL(MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH(MIN) and VIL(MAX) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(MAX) limit insures that tRAC(MAX) and be met. tRCD(MAX) is specified as a reference point only. If tRCD is greater than the specified tRCD(MAX) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD > tRCD(MAX). 6. tOFF(MIN) and tOEZ(MAX) define the time at which the output achieves the open circuit condition and are not referenced VOH or VOL. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS(MIN), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD > tCWD(MIN), tRWD > tRWD(MIN) and tAWD > tAWD(MIN), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. (Continued on page 7)
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
NOTES (continued):
8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS\ falling edge in early write cycles and to W\ falling edge in read-modify-write cycles. 10. Operation within the tRAD(MAX) limit insures that tRAC(MAX) can be met. tRAD(MAX) is specified as a reference point only. If tRAD is greater than the specified tRAS(MAX) limit, then access time is controlled by tAA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. If tRASS > 100 us, then RAS\ precharge time must use tRPS instead of tRP. 14. For RAS\-only refresh and burst CAS\-before-RAS\ refresh mode, 2048 cycles of burst refresh must be executed within 32ms before and after self refresh, in order to meet refresh specification. 15. For distributed CAS\-before-RAS\ with 15.6us interval CAS\-before-RAS\ refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
AS4C4M4
READ CYCLE
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
WRITE CYCLE (EARLY WRITE) DOUT = OPEN
AS4C4M4
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
WRITE CYCLE (OE\ CONTROLLED WRITE) DOUT = OPEN
AS4C4M4
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
READ-MODIFY-WRITE CYCLE
AS4C4M4
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
FAST PAGE READ CYCLE
AS4C4M4
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
FAST PAGE WRITE CYCLE (EARLY WRITE) DOUT = OPEN
AS4C4M4
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
FAST PAGE READ-MODIFY-WRITE CYCLE
AS4C4M4
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
AS4C4M4
RAS\-ONLY REFRESH CYCLE (W\, OE\, DIN = DON'T CARE; DOUT = OPEN)
CAS\-BEFORE-RAS\ REFRESH CYCLE (OE\, A = DON'T CARE)
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
14
Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
HIDDEN REFRESH CYCLE (READ)
AS4C4M4
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
HIDDEN REFRESH CYCLE (WRITE) DOUT = OPEN
AS4C4M4
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
AS4C4M4
CAS\-BEFORE-RAS\ SELF REFRESH CYCLE (OE\, A = DON'T CARE)
TEST MODE IN CYCLE (OE\, A = DON'T CARE)
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
AS4C4M4
MECHANICAL DEFINITIONS*
Package Designator DG
*All measurements are in inches (millimeters).
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Meg 16 Me g FPM DRAM
Austin Semiconductor, Inc.
AS4C4M4
ORDERING INFORMATION
EXAMPLE:
AS4C4M4DG-7/IT
Speed -6 -7 Process /* /*
Device Number Package Type AS4C4M4 AS4C4M4 DG DG
*AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Military Temperature Range
-40oC to +85oC -55oC to +125oC
AS4C4M4 Rev. 1.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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